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1996 microchip technology inc. advance information ds40139a-page 1 devices included in this data sheet: pic12c508 and pic12c509 are 8-bit microcontrollers packaged in 8-lead packages. they are based on the enhanced pic16c5x family. high-performance risc cpu: only 33 single word instructions to learn all instructions are single cycle (1 m s) except for program branches which are two-cycle operating speed: dc - 4 mhz clock input dc - 1 m s instruction cycle 12-bit wide instructions 8-bit wide data path seven special function hardware registers two-level deep hardware stack direct, indirect and relative addressing modes for data and instructions internal 4 mhz rc oscillator with programmable calibration in-circuit serial programming peripheral features: 8-bit real time clock/counter (tmr0) with 8-bit programmable prescaler power-on reset (por) device reset timer (drt) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code-protection power saving sleep mode wake-up from sleep on pin change internal pull-ups on i/o pins selectable oscillator options: - intrc: internal 4 mhz rc oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - lp: power saving, low frequency crystal internal pull-up on mclr pin device eprom ram pic12c508 512 x 12 25 pic12c509 1024 x 12 41 cmos technology: low power, high speed cmos eprom technology fully static design wide operating voltage range: - commercial: 2.5v to 5.5v - industrial: 2.5v to 5.5v low power consumption - < 2 ma @ 5v, 4 mhz - 15 m a typical @ 3v, 32 khz - < 1 m a typical standby current pin diagram pdip, soic 8 7 6 5 1 2 3 4 pic12c508 v ss gp0 gp1 gp2/t0cki pic12c509 gp5/osc1/clkin gp4/osc2 gp3/mclr /v pp vdd pic12c5xx 8-pin, 8-bit cmos microcontroller this document was created with framemake r404
pic12c5xx ds40139a-page 2 advance information 1996 microchip technology inc. table of contents 1.0 general description ..........................................................................................................................................3 2.0 pic12c5xx device varieties............................................................................................................................5 3.0 architectural overview ......................................................................................................................................7 4.0 memory organization......................................................................................................................................11 5.0 i/o port............................................................................................................................................................19 6.0 timer0 module and tmr0 register................................................................................................................21 7.0 special features of the cpu ..........................................................................................................................25 8.0 instruction set summary.................................................................................................................................37 9.0 development support .....................................................................................................................................49 10.0 electrical characteristics - pic12c5xx ..........................................................................................................53 11.0 packaging information ....................................................................................................................................65 appendix a:pic16/17 microcontrollers..........................................................................................................................69 index..............................................................................................................................................................................79 pic12c5xx product identification system ...................................................................................................................83 to our valued customers we constantly strive to improve the quality of all our products and documentation. we have spent an exceptional amount of time to ensure that these documents are correct. however, we realize that we may have missed a few things. if you ?d any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. we appreciate your assistance in making this a better document.
1996 microchip technology inc. advance information ds40139a-page 3 pic12c5xx 1.0 general description the pic12c5xx from microchip technology is a family of low-cost, high performance, 8-bit, fully static, eprom/rom-based cmos microcontrollers. it employs a risc architecture with only 33 single word/ single cycle instructions. all instructions are single cycle (1 m s) except for program branches which take two cycles. the pic12c5xx delivers performance an order of magnitude higher than its competitors in the same price category. the 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. the easy to use and easy to remember instruction set reduces development time signi?antly. the pic12c5xx products are equipped with special features that reduce system cost and power require- ments. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset cir- cuitry. there are four oscillator con?urations to choose from, including intrc internal oscillator mode and the power-saving lp (low power) oscillator. power saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the pic12c5xx are available in the cost-effective one-time-programmable (otp) versions which are suitable for production in any volume. the customer can take full advantage of microchips price leadership in otp microcontrollers while bene?ing from the otps ?xibility. the pic12c5xx products are supported by a full-fea- tured macro assembler, a software simulator, an in-cir- cuit emulator, a ? compiler, fuzzy logic support tools, a low-cost development programmer, and a full fea- tured programmer. all the tools are supported on ibm pc and compatible machines. 1.1 applications the pic12c5xx series ?s perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. the eprom technology makes customizing applica- tion programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and conve- nient. the small footprint packages, for through hole or surface mounting, make this microcontroller series per- fect for applications with space limitations. low-cost, low-power, high performance, ease of use and i/o ?x- ibility make the pic12c5xx series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of ?lue?logic and plds in larger systems, coproces- sor applications).
pic12c5xx ds40139a-page 4 advance information 1996 microchip technology inc. table 1-1: pic12c5xx family of devices pic12c508 4 512 25 tmr0 yes 5 1 yes 2.5-5.5 yes 33 8-pin pdip, 8-pin soic pic12c509 4 1024 41 tmr0 yes 5 1 yes 2.5-5.5 yes 33 8-pin pdip, 8-pin soic all pic12c5xx devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic12c5xx devices use serial programming with data pin gp0 and clock pin gp1. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) wake-up from sleep on pin change i/o pins voltage range (volts) number of instructions packages program memory clock memory peripherals features in-circuit serial programming input pins internal pull-ups
1996 microchip technology inc. advance information ds40139a-page 5 pic12c5xx 2.0 pic12c5xx device varieties a variety of packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic12c5xx product identi?ation system at the back of this data sheet to specify the correct part number. 2.1 one-time-pr ogrammab le (o tp) de vices the availability of otp devices is especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic packages, permit the user to program them once. in addition to the program memory, the con?uration bits must be programmed.
pic12c5xx ds40139a-page 6 advance information 1996 microchip technology inc. notes:
1996 microchip technology inc. advance information ds40139a-page 7 pic12c5xx 3.0 architectural overview the high performance of the pic12c5xx family can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic12c5xx uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architecture where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12-bits wide making it possible to have all single word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions (33) execute in a single cycle (1 m s @ 4mhz) except for program branches. the pic12c508 address 512 x 12 of program memory, the pic12c509 addresses 1k x 12 of program memory. all program memory is internal. the pic12c5xx can directly or indirectly address its register ?es and data memory. all special function registers including the program counter are mapped in the data memory. the pic12c5xx has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?pecial optimal situations make programming with the pic12c5xx simple yet ef?ient. in addition, the learning curve is reduced signi?antly. the pic12c5xx device contains an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register ?e. the alu is 8-bits wide and capable of addition, subtraction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, typically one operand is the w (working) register. the other operand is either a ?e register or an immediate constant. in single operand instructions, the operand is either the w register or a ?e register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the subwf and addwf instructions for examples. a simpli?d block diagram is shown in figure 3-1, with the corresponding device pins described in table 3-1.
pic12c5xx ds40139a-page 8 advance information 1996 microchip technology inc. figure 3-1: pic12c5xx block diagram device reset timer power-on reset watchdog timer eprom program memory 12 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 5 ram addr (1) 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode & control timing generation osc1/clkin osc2 mclr v dd , v ss timer0 gpio 8 8 gp4/osc2 gp3/mclr /vpp gp2/t0cki gp1 gp0 5-7 3 gp5/osc1/clkin stack1 stack2 512 x 12 or 25 x 8 or 1024 x 12 41 x 8 on-chip osc
1996 microchip technology inc. advance information ds40139a-page 9 pic12c5xx table 3-1: pic12c5xx pinout description name dip pin # soic pin # i/o/p type buffer type description gp0 7 7 i/o ttl/st bi-directional i/o port/ serial programming clock. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. this buffer is a schmitt trigger input when used in serial programming mode. gp1 6 6 i/o ttl/st bi-directional i/o port/ serial programming data. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. this buffer is a schmitt trigger input when used in serial programming mode. gp2/t0cki 5 5 i/o st bi-directional i/o port. can be con?ured as t0cki. gp3/mclr /v pp 4 4 i ttl input port/master clear (reset) input/programming volt- age input. when con?ured as mclr , this pin is an active low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. weak pull- up always on if con?ured as mclr gp4/osc2 3 3 i/o ttl bi-directional i/o port/oscillator crystal output. con- nections to crystal or resonator in crystal oscillator mode (xt and lp modes only, gpio in other modes). gp5/osc1/clkin 2 2 i/o ttl/st bidirectional io port oscillator crystal input/external clock source input (gpio in internal rc mode only, osc1 in all other oscillator modes). v dd 1 1 p positive supply for logic and i/o pins v ss 8 8 p ground reference for logic and i/o pins legend: i = input, o = output, i/o = input/output, p = power, ?= not used, ttl = ttl input, st = schmitt trigger input
pic12c5xx ds40139a-page 10 advance information 1996 microchip technology inc. 3.1 cloc king sc heme/ instruction cyc le the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the program counter is incremented every q1, and the instruction is fetched from program memory and latched into instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution ?w is shown in figure 3-2 and example 3-1. 3.2 instruction flo w/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2 (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ushed?from the pipeline while the new instruction is being fetched and then executed. 1. movlw 03h fetch 1 execute 1 2. movwf gpio fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf gpio, bit1 fetch 4 flush fetch sub_1 execute sub_1
1996 microchip technology inc. advance information ds40139a-page 11 pic12c5xx 4.0 memory organization pic12c5xx memory is organized into program mem- ory and data memory. for devices with more than 512 bytes of program memory, a paging scheme is used. program memory pages are accessed using one sta- tus register bit. for the pic12c509 with a data mem- ory register ?e of more than 32 registers, a banking scheme is used. data memory banks are accessed using the file select register (fsr). 4.1 pr ogram memor y or ganization the pic12c508 and pic12c509 each have a 12-bit program counter (pc) capable of addressing a 2k x 12 program memory space. only the ?st 512 x 12 (0000h-01ffh) for the pic12c508 and 1k x 12 (0000h-03ffh) for the pic12c509 are physically implemented. refer to figure 4-1. accessing a location above these boundaries will cause a wrap-around within the ?st 512 x 12 space (pic12c508) or 1k x 12 space (pic12c509). the reset vector is at 0000h. location 01ffh (pic12c508) or location 03ffh (pic12c509) contains the internal clock oscillator calibration value. this value should never be overwritten. figure 4-1: program memory map and stack for the pic12c5xx call, retlw pc<11:0> stack level 1 stack level 2 user memory space 12 0000h 7ffh 01ffh 0200h on-chip program memory reset vector (note 1) note 1: address 0000h becomes the effec- tive reset vector. location 01ffh (pic12c508) or location 03ffh (pic12c509) contains the movlw xx clock calibration value. 512 word (pic12c508) 1024 word (pic12c509) 03ffh 0400h on-chip program memory
pic12c5xx ds40139a-page 12 advance information 1996 microchip technology inc. 4.2 data memor y or ganization data memory is composed of registers, or bytes of ram. therefore, data memory for a device is speci?d by its register ?e. the register ?e is divided into two functional groups: special function registers and general purpose registers. the special function registers include the tmr0 register, the program counter (pc), the status register, the i/o registers (ports), and the file select register (fsr). in addition, special purpose registers are used to control the i/o port con?uration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic12c508, the register ?e is composed of 7 special function registers and 25 general purpose registers (figure 4-2). for the pic12c509, the register ?e is composed of 7 special function registers, 25 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (figure 4-3). 4.2.1 general purpose register file the general purpose register ?e is accessed either directly or indirectly through the ?e select register fsr (section 4.7). figure 4-2: pic12c508 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal gpio general purpose registers note 1: not a physical register. see section 4.7 figure 4-3: pic12c509 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal gpio 0fh 10h bank 0 bank 1 3fh 30h 20h 2fh general purpose registers general purpose registers general purpose registers addresses map back to addresses in bank 0. note 1: not a physical register. see section 4.7 fsr<6:5> 00 01
1996 microchip technology inc. advance information ds40139a-page 13 pic12c5xx 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions to control the operation of the device (table 4-1). the special registers can be classi?d into two sets. the special function registers associated with the ?ore?functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. table 4-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on m clr and wdt reset value on wake-up on pin change n/a tris i/o control registers --11 1111 --11 1111 --11 1111 n/a option contains control bits to con?ure timer0, timer0/wdt prescaler, interrupt on change, and weak pull-ups 1111 1111 1111 1111 1111 1111 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu uuuu uuuu 01h tmr0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu uuuu uuuu 02h (1) pcl low order 8 bits of pc 1111 1111 1111 1111 1111 1111 03h status gpwuf pa0 t o pd zdcc 0001 1xxx 000q quuu 100q quuu 04h fsr (12c508) indirect data memory address pointer 111x xxxx 111u uuuu 111u uuuu 04h fsr (12c509) indirect data memory address pointer 110x xxxx 11uu uuuu 11uu uuuu 04h fsr indirect data memory address pointer 1xxx xxxx 1uuu uuuu 1uuu uuuu 05h osccal cal7 cal6 cal5 cal4 0111 ---- uuuu ---- uuuu ---- 06h gpio gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx --uu uuuu --uu uuuu legend: shaded boxes = unimplemented or unused, = unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in section 7.7 for possible values. note 1: the upper byte of the program counter is not directly accessible. see section 4.5 for an explanation of how to access these bits.
pic12c5xx ds40139a-page 14 advance information 1996 microchip technology inc. 4.3 s t a tus register this register contains the arithmetic status of the alu, the reset status, and the page preselect bit for program memories larger than 512 words. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the t o and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf and movwf instructions be used to alter the status register because these instructions do not affect the z, dc or c bits from the status register. for other instructions, which do affect status bits, see table 8- 2, instruction set summary. figure 4-4: status register (address:03h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x gpwuf pa0 t o pd z dc c r = readable bit w = writable bit - n = value at por reset bit7 6 5 4 3 2 1 bit0 bit 7: gpwuf : gpio reset bit 1 = reset from wake-up from sleep on pin change 0 = after power up or other reset bit 6: unimplemented bit 5: pa0 : program page preselect bits 1 = page 1 (200h - 3ffh) - pic12c509 0 = page 0 (000h - 1ffh) - pic12c508 and pic12c509 each page is 512 bytes. using the pa0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit (for addwf and subwf instructions) addwf 1 = a carry from the 4th low order bit of the result occurred 0 = a carry from the 4th low order bit of the result did not occur subwf 1 = a borrow from the 4th low order bit of the result did not occur 0 = a borrow from the 4th low order bit of the result occurred bit 0: c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf subwf rrf or rlf 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred
1996 microchip technology inc. advance information ds40139a-page 15 pic12c5xx 4.4 o ption register the option register is a 8-bit wide, write-only register which contains various control bits to con?ure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option register. a reset sets the option<7:0> bits. note that tris overrides option control if gppu is enabled and gpwu is disabled. note: if tris bit is set to ?? the wake-up on change and pull-up functions are disabled for that pin. note: if the tocs bit is set to ?? gp2 is forced to be an input even if tris gp2 = ? figure 4-5: option register w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 gpwu gppu t0cs t0se psa ps2 ps1 ps0 w = writable bit u = unimplemented bit - n = value at por reset reference table 4-1 for other resets. bit7 6 5 4 3 2 1 bit0 bit 7: gpwu : enable wake-up on pin change (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 6: gppu : enable weak pull-ups (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 5: t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = transition on internal instruction cycle clock, fosc/4 bit 4: t0se : timer0 source edge select bit 1 = increment on high to low transition on the t0cki pin 0 = increment on low to high transition on the t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
pic12c5xx ds40139a-page 16 advanced information 1996 microchip technology inc. 4.5 pr ogram counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the pc latch (pcl) is mapped to pc<7:0>. bit 5 of the status register provides page information to bit 9 of the pc (figure 4- 6). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc again are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-6). instructions where the pcl is the destination, or modify pcl instructions, include movwf pc, addwf pc, and bsf pc,5. figure 4-6: loading of pc branch instructions - pic12c508/c509 note: because pc<8> is cleared in the call instruction, or any modify pcl instruction, all subroutine calls or computed jumps are limited to the ?st 256 locations of any pro- gram memory page (512 words long). pa0 status pc 87 0 pcl 9 10 instruction word 70 goto instruction call or modify pcl instruction 11 pa0 status pc 87 0 pcl 9 10 instruction word 70 11 reset to ? 4.5.1 effects of reset the program counter is set upon a reset, which means that the pc addresses the last location in the last page i.e., the oscillator calibration instruction. after executing movlw xx, the pc will roll over to location 00h, and begin executing user code. the status register page preselect bits are cleared upon a reset, which means that page 0 is pre- selected. therefore, upon a reset, a goto instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 4.6 s tac k pic12c5xx devices have a 12-bit wide hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. if more than two sequential call s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. if more than two sequential retlw s are executed, the stack will be filled with the address previously stored in level 2. note that the w register will be loaded with the literal value speci?d in the instruction. this is particularly useful for the implementation of data look-up tables within the program memory.
1996 microchip technology inc. advance information ds40139a-page 17 pic12c5xx 4.7 indirect data ad dressing; indf and fsr register s the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 4-1: indirect addressing register ?e 07 contains the value 10h register ?e 08 contains the value 0ah load the value 07 into the fsr register a read of the indf register will return the value of 10h increment the value of the fsr register by one (fsr = 08) a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-2. example 4-2: how to clear ram using indirect addressing movlw 0x10 ;initialize pointer movwf fsr ; to ram next clrf indf ; clear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue the fsr is a 5-bit wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. pic12c508: does not use banking. fsr<6:5> are unimplemented and read as '1's. pic12c509: uses fsr<5>. selects between bank 0 and bank 1. fsr<6> is unimplemented, read as '1 . figure 4-7: direct/indirect addressing note 1: for register map detail see section 4.2. note 2: pic12c509 only bank location select location select bank select indirect addressing direct addressing data memory (1) 0fh 10h bank 0 bank 1 (2) 0 4 5 6 (fsr) 00 01 00h 1fh 3fh (opcode) 0 4 5 6 (fsr) addresses map back to addresses in bank 0.
pic12c5xx ds40139a-page 18 advance information 1996 microchip technology inc. notes:
1996 microchip technology inc. advance information ds40139a-page 19 pic12c5xx 5.0 i/o port as with any other register, the i/o register can be written and read under program control. however, read instructions (e.g., movf gpio,w ) always read the i/o pins independent of the pins input/output modes. on reset, all i/o ports are de?ed as input (inputs are at hi-impedance) since the i/o control registers are all set. gp0 and gp1 can be programmed in software with weak pull-ups. 5.1 gpio gpio is an 8-bit i/o register. only the low order 6 bits are used (gp5:gp0). bits 7 and 6 are unimplemented and read as '0's. please note that gp3 is an input only pin. the con?uration word can set several i/os to alternate functions. when acting as alternate functions the pins will read as ? during port read. pins gp0, gp1, and gp3 can be con?ured with weak pull-ups and also with wake-up on change. the wake-up on change and weak pull-up functions are not pin selectable. if pin 4 is con?ured as mclr , weak pull- up is always on and wake-up on change for this pin is not set. 5.2 tris register the output driver control register is loaded with the contents of the w register by executing the tris f instruction. a '1' from a tris register bit puts the corresponding output driver in a hi-impedance mode. a '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. the exceptions are gp3 which is input only and gp2 which may be controlled by the option register, see section 4.4. the tris registers are ?rite-only?and are set (output drivers disabled) upon reset. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. 5.3 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-1. all port pins, except gp3 which is input only, may be used for both input and output operations. for input operations these ports are non- latching. any input must be present until read by an input instruction (e.g., movf gpio,w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corresponding direction control bit in tris must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin (except gp3) can be programmed individually as input or output. figure 5-1: equivalent circuit for a single i/o pin note 1: i/o pins have protection diodes to v dd and v ss . data bus q d q ck q d q ck p n wr port tris ? data tris rd port v ss v dd i/o pin (1) w reg latch latch reset table 5-1: summary of port registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on m clr and wdt reset value on wake-up on pin change n/a tris i/o control registers --11 1111 --11 1111 --11 1111 n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 1111 1111 03h status gpwuf pa0 t o pd zdcc 0001 1xxx 000q quuu 100q quuu 06h gpio gp5 gp4 gp3 gp2 gp1 gp0 --xx xxxx --uu uuuu --uu uuuu legend: shaded cells not used by port registers, read as ?? ?= unimplemented, read as '0', x = unknown, u = unchanged, q = see tables in section 7.7 for possible values.
pic12c5xx ds40139a-page 20 advance information 1996 microchip technology inc. 5.4 i/o pr ogramming considerations 5.4.1 bi-directional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit5 of gpio will cause all eight bits of gpio to be read into the cpu, bit5 to be set and the gpio value to be written to the output latches. if another bit of gpio is used as a bi- directional i/o pin (say bit0) and it is de?ed as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read- modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (?ired-or? ?ired- and?. the resulting high output currents may damage the chip. example 5-1: read-modify-write instructions on an i/o port ;initial gpio settings ; gpio<5:3> inputs ; gpio<2:0> outputs ;gpio<6> have external pull-ups and are ;not connected to other circuitry ; ; gpio latch gpio pins ; ---------- ---------- bcf gpio, 5 ;--01 -ppp --11 pppp bcf gpio, 4 ;--10 -ppp --11 pppp movlw 007h ; tris gpio ;--10 -ppp --11 pppp ; ;note that the user may have expected the pin ;values to be --00 pppp. the 2nd bcf caused ;gp4 to be latched as the pin value (high). 5.4.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-2). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that ?e to be read into the cpu, is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched gp5:gp0 movwf gpio nop port pin sampled here nop movf gpio,w instruction executed movwf gpio (write to gpio) nop movf gpio,w this example shows a write to gpio followed by a read from gpio. data setup time = (0.25 t cy ?t pd ) where: t cy = instruction cycle. t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read gpio) port pin written here
1996 microchip technology inc. advance information ds40139a-page 21 pic12c5xx 6.0 timer0 module and tmr0 register the timer0 module has the following features: 8-bit timer/counter register, tmr0 - readable and writable 8-bit software programmable prescaler internal or external clock select - edge select for external clock figure 6-1 is a simpli?d block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the t0se bit (option<4>) determines the source edge. clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.1. the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 6.2 details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. figure 6-1: timer0 block diagram note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-5). 0 1 1 0 t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg psout (2 cycle delay) psout data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync t0se gp2/t0cki pin
pic12c5xx ds40139a-page 22 advance information 1996 microchip technology inc. figure 6-2: timer0 timing: internal clock/no prescale figure 6-3: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on m clr and wdt reset value on wake-up on pin change 01h tmr0 timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu uuuu uuuu n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 1111 1111 n/a tris i/o control registers --11 1111 --11 1111 --11 1111 legend: shaded cells not used by timer0, - = unimplemented, x = unknown, u = unchanged, pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t0
1996 microchip technology inc. advance information ds40139a-page 23 pic12c5xx 6.1 using t imer0 with an external cloc k when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-4). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical speci?ation of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of 10 ns. refer to parameters 40, 41 and 42 in the electrical speci?ation of the desired device. 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 6-4 shows the delay from the external clock edge to the timer incrementing. 6.1.3 option register effect on gp2 tris if the option register is set to read timer0 from the pin, the port is forced to an input regardless of the tris reg- ister setting. figure 6-4: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) note 1: 2: 3: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. external clock if no prescaler selected, prescaler output otherwise. the arrows indicate the points in time where sampling occurs. prescaler output (2) (1)
pic12c5xx ds40139a-page 24 advance information 1996 microchip technology inc. 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer (wdt), respectively (section 7.6). for simplicity, this counter is being referred to as ?rescaler throughout this data sheet. note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the psa and ps2:ps0 bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all '0's. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?n the ??during program execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 ? wdt) clrf tmr0 ;clear tmr0 clrwdt ;clears wdt and ;prescaler movlw 'xxxx1xxx' ;select new prescale option ;value to change prescaler from the wdt to the timer0 module, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 6-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler movlw 'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option figure 6-5: block diagram of the timer0/wdt prescaler t cy ( = fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m mux watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are bits in the option register. psa wdt enable bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x t0se gp2/t0cki pin
1996 microchip technology inc. advance information ds40139a-page 25 pic12c5xx 7.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. the pic12c5xx family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these features are: oscillator selection reset - power-on reset (por) - device reset timer (drt) - wake-up from sleep on pin change watchdog timer (wdt) sleep code protection id locations in-circuit serial programming the pic12c5xx has a watchdog timer which can be shut off only through con?uration bit wdte. it runs off of its own rc oscillator for added reliability. if using xt or lp selectable oscillator options, there is always an 18 ms delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. if using intrc or extrc there is an 18 ms delay only on v dd power-up. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through a change on input pins or through a watchdog timer time-out. several oscillator options are also made available to allow the part to ? the application, including an internal 4 mhz oscillator. the extrl rc oscillator option saves system cost while the lp crystal option saves power. a set of con?uration bits are used to select various options. 7.1 con guration bits the pic12c5xx con?uration word consists of 5 bits. con?uration bits can be programmed to select various device con?urations. two bits are for the selection of the oscillator type, one bit is the watchdog timer enable bit, and one bit is the mclr enable bit. one bit is the code protection bit (figure 7-1). otp devices have the oscillator con?uration programmed at the factory and these parts are tested accordingly (see ?roduct identi?ation system?on the inside back cover). figure 7-1: configuration word for pic12c508 or pic12c509 mclre cp wdte fosc1 fosc0 register: config address (1) : fffh bit11 10 987654321 bit0 bit 11-5: unimplemented bit 4: mclre: mclr enable bit. 1 = mclr enabled 0 = mclr disabled bit 3: cp: code protection bit. 1 = code protection off 0 = code protection on bit 2: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0: oscillator selection bits 11 = extrc - external rc oscillator 10 = intrc - internal rc oscillator 01 = xt oscillator 00 = lp oscillator note 1: refer to the pic12c5xx programming speci?ations to determine how to access the con?uration word. this register is not user addressable during device operation.
pic12c5xx ds40139a-page 26 advanced information 1996 microchip technology inc. 7.2 oscillator con gurations 7.2.1 oscillator types the pic12c5xx can be operated in four different oscillator modes. the user can program two con?uration bits (fosc1:fosc0) to select one of these four modes: lp: low power crystal xt: crystal/resonator intrc: internal 4 mhz oscillator extrc: external resistor/capacitor 7.2.2 crystal oscillator / ceramic resonators in xt or lp modes, a crystal or ceramic resonator is connected to the gp5/osc1/clkin and gp4/osc2 pins to establish oscillation (figure 7-2). the pic12c5xx oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?ations. when in xt or lp modes, the device can have an external clock source drive the gp5/ osc1/clkin pin (figure 7-3). figure 7-2: crystal operation (or ceramic resonator) (xt or lp osc configuration) figure 7-3: external clock input operation (xt or lp osc configuration) note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen (approx. value = 10 m w ). c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic12c5xx clock from ext. system osc1 osc2 pic12c5xx open table 7-1: capacitor selection for ceramic resonators - pic12c5xx table 7-2: capacitor selection for crystal oscillator - pic12c5xx osc type resonator freq cap. range c1 cap. range c2 xt 455 khz 2.0 mhz 4.0 mhz 68-100 pf 15-33 pf 10-22 pf 68-100 pf 15-33 pf 10-22 pf these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. osc type resonator freq cap.range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15 pf 15 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15 pf 15 pf note 1: for v dd > 4.5v, c1 = c2 ? 30 pf is recommended. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci?ation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
1996 microchip technology inc. advance information ds40139a-page 27 pic12c5xx 7.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crystal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 7-4 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potentiometers bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 7-4: external parallel resonant crystal oscillator circuit figure 7-5 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180- degree phase shift in a series resonant oscillator circuit. the 330 w resistors provide the negative feedback to bias the inverters in their linear region. figure 7-5: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic12c5xx clkin to other devices 330 74as04 74as04 pic12c5xx clkin to other devices xtal 330 74as04 0.1 m f 7.2.4 external rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (rext) and capacitor (cext) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 7-6 shows how the r/c combination is connected to the pic12c5xx. for rext values below 2.2 k w , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g., 1 m w ) the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. the electrical speci?ations sections show rc frequency variation from part to part due to normal process variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). also, see the electrical speci?ations sections for variation of oscillator frequency due to v dd for given rext/cext values as well as frequency variation due to operating temperature for given r, c, and v dd values.
pic12c5xx ds40139a-page 28 advance information 1996 microchip technology inc. figure 7-6: rc oscillator mode 7.2.5 internal 4 mhz rc oscillator the internal rc oscillator provides a ?ed 4 mhz (nom- inal) system clock. in addition, a calibration instruction is programmed into the top of memory which indicates the calibration value for the internal rc oscillator. this value, osccal, is programmed as a movlw xx instruction where xx is the calibration value, and is placed at the reset vector. this will load the w register with the calibration value upon reset and the pc will then roll over to 0x000. the user then has the option of writing the value to the osccal register (05h) or ignoring it. v dd rext cext v ss osc1 internal clock pic12c5xx n 7.3 reset the device differentiates between various kinds of reset: a) power on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) wdt time-out reset during normal operation e) wdt time-out reset during sleep f) wake-up from sleep on pin change some registers are not reset in any way; they are unknown on por and unchanged in any other reset. most other registers are reset to ?eset state?on power- on reset (por), on mclr or wdt reset during normal operation . they are not affected by a wdt reset during sleep or mclr reset during sleep, since these resets are viewed as resumption of normal operation. the exceptions to this are t o , pd , and gpwuf bits. they are set or cleared differently in different reset sit- uations. these bits are used in software to determine the nature of reset. see table 7-3 for a full description of reset states of all registers. table 7-3: reset conditions for registers register address power-on reset mclr reset wdt time-out wake-up on pin change w qqqq xxxx (1) qqqq uuuu (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pc 02h 1111 1111 1111 1111 status 03h 0001 1xxx ?00? ?uuu (2) fsr (12c508) 04h 111x xxxx 111u uuuu fsr (12c509) 04h 110x xxxx 11uu uuuu osccal 05h 0111 ---- uuuu ---- gpio 06h --xx xxxx --uu uuuu option 1111 1111 1111 1111 tris --11 1111 --11 1111 legend: u = unchanged, x = unknown, - = unimplemented bit, read as ?? ? = value depends on condition. note 1: bits <7:4> of w register contain oscillator calibration (osccal) values due to movlw xx instruction at top of memory. note 2: see table 7-6 for reset value for speci? conditions
1996 microchip technology inc. advance information ds40139a-page 29 pic12c5xx table 7-4: reset condition for special registers status addr: 03h pcl addr: 02h power on reset 0001 1xxx 1111 1111 mclr reset during normal operation 000u uuuu 1111 1111 mclr reset during sleep 0001 0uuuu 1111 1111 wdt reset during sleep 0000 0uuu 1111 1111 wdt reset normal operation 0000 1uuu 1111 1111 wake-up from sleep on pin change 1001 0uuu 1111 1111 legend: u = unchanged, x = unknown, - = unimplemented bit, read as ?? 7.3.1 mclr enable this con?uration bit when unprogrammed (left in the ? state) enables the external mclr function. when programmed, the mclr function is tied to the internal v dd , and the pin is assigned to be a gpio. see figure 7-7. figure 7-7: mclr select 7.4 p o wer -on reset ( por) the pic12c5xx family incorporates on-chip power- on reset (por) circuitry which provides an internal chip reset for most power-up situations. a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.5v - 2.1v). to take advantage of the por, tie the mclr pin directly to v dd . an internal weak pull-up resistor is imple- mented using a transistor. refer to table 10-5 for the pull-up resistor ranges. this will eliminate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is speci?d. see electrical speci?ations for details. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating parameters are met. a simpli?d block diagram of the on-chip power-on reset circuit is shown in figure 7-8. gp3/mclr /v pp mclre internal mclr weak pull-up the power-on reset circuit and the device reset timer (section 7.5) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on- chip reset signal. a power-up example where mclr is tied to v ss is shown in figure 7-9. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 7-10, the on-chip power-on reset feature is being used (mclr and v dd are tied together). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 7-11 depicts a problem situation where v dd rises too slowly. the time between when the drt senses a high on the gp3/m clr /v pp pin, and when the gp3/m clr /v pp pin (and v dd ) actually reach their full value, is too long. in this situation, when the start- up timer times out, v dd has not reached the v dd (min) value and the chip is, therefore, not guaranteed to function correctly. for such situations, we recommend that external rc circuits be used to achieve longer por delay times (figure 7-10). for additional information refer to application notes power-up considerations - an522 and power-up trouble shooting ?- an607. note: when the device starts normal operation (exits the reset condition), device operat- ing parameters (voltage, frequency, tem- perature, etc.) must be meet to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met.
pic12c5xx ds40139a-page 30 advance information 1996 microchip technology inc. figure 7-8: simplified block diagram of on-chip reset circuit sq r q v dd gp3/m clr /v pp power-up detect on-chip drt osc por (power-on reset) wdt time-out reset chip reset 8-bit asynch ripple counter (start-up timer) mclre sleep pin change wake-up on pin change
1996 microchip technology inc. advance information ds40139a-page 31 pic12c5xx figure 7-9: time-out sequence on power-up (mclr pulled low) figure 7-10: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time figure 7-11: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v1 when v dd rises slowly, the t drt time-out expires long before v dd has reached its ?al value. in this example, the chip will reset properly if, and only if, v1 3 v dd min.
pic12c5xx ds40139a-page 32 advanced information 1996 microchip technology inc. 7.5 de vice reset timer (dr t) in the pic12c5xx, the drt runs any time the device is powered up. drt runs from reset only in xt and lp modes. it is disabled from reset in intrc and extrc modes. the device reset timer (drt) provides a ?ed 18 ms nominal time-out on reset. the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min., and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset condition for approximately 18 ms after the voltage on the gp3/m clr /v pp pin has reached a logic high (v ihmc ) level. thus, external rc networks connected to the mclr input are not required in most cases, allowing for savings in cost- sensitive and/or space restricted applications. the device reset time delay will vary from chip to chip due to v dd , temperature, and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out (only in xt and lp modes). this is particularly important for applications using the wdt to wake from sleep mode automatically. 7.6 w atc hdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the external rc oscillator of the gp5/osc1/clkin pin and the internal 4 mhz oscillator. that means that the wdt will run even if the clock on the gp5/osc1/ clkin and gp4/osc2 pins have been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset generates a device reset. the t o bit (status<4>) will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by programming the con?uration bit wdte as a '0' (section 7.1). refer to the pic12c5xx programming speci?ations to determine how to access the con?uration word.
1996 microchip technology inc. advance information ds40139a-page 33 pic12c5xx 7.6.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writing to the option register. thus, time-out a period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to- part process variations (see dc specs). under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 7.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. figure 7-12: watchdog timer block diagram table 7-5: summary of registers associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on m clr and wdt reset value on wake-up on pin change n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 1111 1111 legend: shaded boxes = not used by watchdog timer, = unimplemented, read as '0', u = unchanged 1 0 1 0 from timer0 clock source (figure 6-5) to timer0 (figure 6-4) postscaler wdt enable eprom bit psa wdt time-out ps2:ps0 psa mux 8 - to - 1 mux postscaler m u x watchdog timer note: t0cs, t0se, psa, ps2:ps0 are bits in the option register.
pic12c5xx ds40139a-page 34 advanced information 1996 microchip technology inc. 7.7 time-out sequence , p o wer do wn , and w ake-up fr om sleep s tatus bits ( t o / pd /gpwu f ) the t o , p d , and gpwuf bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset, or a mclr or wdt reset. these status bits are only affected by events listed in table 7-7. table 7-4 lists the reset conditions for the special function registers, while table 7-3 lists the reset conditions for all the registers. table 7-6: t o /pd /gpwuf status after reset gpwuf t o pd reset caused by 000 wdt wake-up from sleep 001 wdt time-out (not from sleep) 010 mclr wake-up from sleep 011 power-up 0uu mclr not during sleep 110 wake-up from sleep on pin change legend: legend: u = unchanged note 1: the t o , p d , and gpwuf bits main- tain their status (u) until a reset occurs. a low-pulse on the mclr input does not change the t o , pd , and gpwuf status bits. table 7-7: events affecting t o /pd status bits event gpwuf t o pd remarks power-up 011 wdt time-out 00u no effect on pd sleep instruction u10 clrwdt instruction u11 wake-up from sleep on pin change 110 legend: u = unchanged a wdt time-out will occur regardless of the status of the t o bit. a sleep instruction will be executed, regardless of the status of the pd bit. table 7-6 re?cts the status of t o and pd after the corresponding event. 7.8 reset on br o wn-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic12c5xx devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 7-13 and figure 7-14. figure 7-13: brown-out protection circuit 1 figure 7-14: brown-out protection circuit 2 this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). *refer to figure 7-7 and table 10-5 for internal weak pull- up on mclr. 33k 10k 40k* v dd mclr pic12c5xx v dd q1 this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: *refer to figure 7-7 and table 10-5 for internal weak pull-up on mclr. v dd r1 r1 + r2 = 0.7v r2 40k v dd mclr pic12c5xx r1 q1 v dd
1996 microchip technology inc. advance information ds40139a-page 35 pic12c5xx 7.9 p o wer -do wn mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 7.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the t o bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low, or hi-impedance). it should be noted that a reset generated by a wdt time-out does not drive the gp3/mclr /v pp pin low. for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the gp3/ mclr /v pp pin must be at a logic high level (v ihmc ) if mclr is enabled. 7.9.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on gp3/mclr /v pp pin. 2. a watchdog timer time-out reset (if wdt was enabled). 3. a change on input pin gp0, gp1, or gp3 these events cause a device reset. the t o , p d , and gpwuf bits can be used to determine the cause of device reset.. the t o bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the gpwuf bit indicates a change in state while in sleep at pins gp0, gp1, or gp3 (since the last time there was a ?e or bit operation on gp port). the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. caution: right before entering sleep, read the input pins. when in sleep, wake up occurs when the values at the pins change from the state they were in at the last reading. if a wake-up on change occurs and the pins are not read before reentering sleep, a wake up will occur immediately even if no pins change while in sleep mode. 7.10 p r ogram v eri cation/code pr otection if the code protection bit has not been programmed, the on-chip program memory can be read out for veri?ation purposes. 7.11 id locations four memory locations are designated as id locations where the user can store checksum or other code- identi?ation numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as '1's.
pic12c5xx ds40139a-page 36 advanced information 1996 microchip technology inc. 7.12 i n-cir cuit serial pr ogramming the pic12c5xx microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent ?mware or a custom ?mware to be programmed. the device is placed into a program/verify mode by holding the gp1 and gp0 pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming speci?ation). gp1 becomes the programming clock and gp0 becomes the programming data. both gp1 and gp0 are schmitt trigger inputs in this mode. after reset, a 6-bit command is then supplied to the device. depending on the command, 14-bits of pro- gram data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic12c5xx programming speci?ations. a typical in-circuit serial programming connection is shown in figure 7-15. figure 7-15: typical in-circuit serial programming connection external connector signals to normal connections to normal connections pic12c5xx v dd v ss mclr /v pp gp1 gp0 +5v 0v v pp clk data i/o v dd
1996 microchip technology inc. advance information ds40139a-page 37 pic12c5xx 8.0 instruction set summary each pic12c5xx instruction is a 12-bit word divided into an opcode, which speci?s the instruction type, and one or more operands which further specify the operation of the instruction. the pic12c5xx instruction set summary in table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. table 8-1 shows the opcode ?ld descriptions. for byte-oriented instructions, 'f' represents a ?e register designator and 'd' represents a destination designator. the ?e register designator is used to specify which one of the 32 file registers is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' is '0', the result is placed in the w register. if 'd' is '1', the result is placed in the ?e register speci?d in the instruction. for bit-oriented instructions, 'b' represents a bit ?ld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. for literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. table 8-1: opcode field descriptions field description f register ?e address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in ?e register 'f') default is d = 1 label label name tos top of stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the speci?d register ?e location [ ] options ( ) contents ? assigned to < > register bit ?ld ? in the set of i talics user de?ed term (font is courier) all instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 m s. figure 8-1 shows the three general formats that the instructions can have. all examples in the ?ure use the following format to represent a hexadecimal number: 0xhhh where 'h' signi?s a hexadecimal digit. figure 8-1: general format for instructions byte-oriented ?e register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit ?e register address bit-oriented ?e register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit ?e register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations - goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value
pic12c5xx ds40139a-page 38 advance information 1996 microchip technology inc. table 8-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f,d f,d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z none z none z z none none c c c,dc,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k k k k k k k f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none t o , pd none z none none none t o , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a '0' by any instruction that writes to the pc except for goto . (section 4.5) 2: when an i/o register is modi?d as a function of itself (e.g. movf gpio, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 3: the instruction tris f , where f = 5, 6, or 7 causes the contents of the w register to be written to the tristate latches of gpio. a '1' forces the pin to a hi-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to tmr0).
1996 microchip technology inc. advance information ds40139a-page 39 pic12c5xx addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d ? [0,1] operation: (w) + (f) ? (dest) status affected: c, dc, z encoding: 0001 11df ffff description: add the contents of the w register and register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f' . words: 1 cycles: 1 example: addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) ? (w) status affected: z encoding: 1110 kkkk kkkk description: the contents of the w register are and?d with the eight-bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example: andlw 0x5f before instruction w = 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d ? [0,1] operation: (w) .and. (f) ? (dest) status affected: z encoding: 0001 01df ffff description: the contents of the w register are and?d with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f' . words: 1 cycles: 1 example: andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 ? (f) status affected: none encoding: 0100 bbbf ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example: bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47
pic12c5xx ds40139a-page 40 advanced information 1996 microchip technology inc. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 ? (f) status affected: none encoding: 0101 bbbf ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example: bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 0110 bbbf ffff description: if bit 'b' in register 'f' is 0 then the next instruction is skipped. if bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and an nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here false true btfsc goto flag,1 process_code before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (true) ; if flag<1> = 1, pc = address (false) btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 0111 bbbf ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and an nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here btfss flag,1 false goto process_code true before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (false) ; if flag<1> = 1, pc = address (true)
1996 microchip technology inc. advance information ds40139a-page 41 pic12c5xx call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 ? top of stack; k ? pc<7:0>; (status<6:5>) ? pc<10:9>; 0 ? pc<8> status affected: none encoding: 1001 kkkk kkkk description: subroutine call. first, return address (pc+1) is pushed onto the stack. the eight bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from sta- tus<6:5>, pc<8> is cleared. call is a two cycle instruction. words: 1 cycles: 2 example: here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h ? (f); 1 ? z status affected: z encoding: 0000 011f ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example: clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w); 1 ? z status affected: z encoding: 0000 0100 0000 description: the w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example: clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt; 0 ? wdt prescaler (if assigned); 1 ? t o; 1 ? pd status affected: t o , pd encoding: 0000 0000 0100 description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits t o and pd are set. words: 1 cycles: 1 example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescale = 0 t o =1 pd =1
pic12c5xx ds40139a-page 42 advanced information 1996 microchip technology inc. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d ? [0,1] operation: (f ) ? (dest) status affected: z encoding: 0010 01df ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d ? [0,1] operation: (f) ?1 ? (dest) status affected: z encoding: 0000 11df ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d ? [0,1] operation: (f) ?1 ? d; skip if result = 0 status affected: none encoding: 0010 11df ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded and an nop is executed instead mak- ing it a two cycle instruction. words: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1; if cnt = 0, pc = address (continue) ; if cnt 1 0, pc = address (here+1) goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k ? pc<8:0>; status<6:5> ? pc<10:9> status affected: none encoding: 101k kkkk kkkk description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two cycle instruction. words: 1 cycles: 2 example: goto there after instruction pc = address (there)
1996 microchip technology inc. advance information ds40139a-page 43 pic12c5xx incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z encoding: 0010 10df ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none encoding: 0011 11df ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, then the next instruc- tion, which is already fetched, is dis- carded and an nop is executed instead making it a two cycle instruc- tion. words: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt + 1; if cnt = 0, pc = address (continue) ; if cnt 1 0, pc = address (here +1) iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) ? (w) status affected: z encoding: 1101 kkkk kkkk description: the contents of the w register are or?d with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: iorlw 0x35 before instruction w = 0x9a after instruction w = 0xbf z=0 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d ? [0,1] operation: (w).or. (f) ? (dest) status affected: z encoding: 0001 00df ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=0
pic12c5xx ds40139a-page 44 advanced information 1996 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 31 d ? [0,1] operation: (f) ? (dest) status affected: z encoding: 0010 00df ffff description: the contents of register 'f' is moved to destination 'd'. if 'd' is 0, destination is the w register. if 'd' is 1, the destination is ?e register 'f'. 'd' is 1 is useful to test a ?e register since status ?g z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none encoding: 1100 kkkk kkkk description: the eight bit literal 'k' is loaded into the w register. the don? cares will assem- ble as 0s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) ? (f) status affected: none encoding: 0000 001f ffff description: move data from the w register to regis- ter 'f' . words: 1 cycles: 1 example: movwf temp_reg before instruction temp_reg = 0xff w = 0x4f after instruction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 description: no operation. words: 1 cycles: 1 example: nop
1996 microchip technology inc. advance information ds40139a-page 45 pic12c5xx option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 0000 0000 0010 description: the content of the w register is loaded into the option register. words: 1 cycles: 1 example option before instruction w = 0x07 after instruction option = 0x07 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none encoding: 1000 kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 example: table call table ;w contains ;table offset ;value. ? ;w now has table ? ;value. addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d ? [0,1] operation: see description below status affected: c encoding: 0011 01df ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 1100 1100 c= 1 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d ? [0,1] operation: see description below status affected: c encoding: 0011 00df ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: rrf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 0111 0011 c= 0 c register 'f' c register 'f'
pic12c5xx ds40139a-page 46 advanced information 1996 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt; 0 ? wdt prescaler; 1 ? t o ; 0 ? pd status affected: t o , pd , gpwuf encoding: 0000 0000 0011 description: time-out status bit (t o ) is set. the power down status bit (pd ) is cleared. gpwuf is unaffected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see sec- tion on sleep for more details. words: 1 cycles: 1 example: sleep subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 31 d ? [0,1] operation: (f) ?(w) ? ( dest) status affected: c, dc, z encoding: 0000 10df ffff description: subtract (2s complement method) the w register from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1 : subwf reg1, 1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1 ; result is positive e xample 2 : before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1 ; result is zero e xample 3 : before instruction reg1 = 1 w=2 c=? after instruction reg1 = ff w=2 c = 0 ; result is negative
1996 microchip technology inc. advance information ds40139a-page 47 pic12c5xx swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>); (f<7:4>) ? (dest<3:0>) status affected: none encoding: 0011 10df ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg1, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: f = 6 operation: (w) ? tris register f status affected: none encoding: 0000 0000 0fff description: tris register 'f' (f = 6) is loaded with the contents of the w register words: 1 cycles: 1 example tris gpio before instruction w = 0xa5 after instruction tris = 0xa5 note: f = 6 for pic12c5xx only. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z encoding: 1111 kkkk kkkk description: the contents of the w register are xor?d with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w = 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d ? [0,1] operation: (w) .xor. (f) ? ( dest) status affected: z encoding: 0001 10df ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg,1 before instruction reg = 0xaf w = 0xb5 after instruction reg = 0x1a w = 0xb5
pic12c5xx ds40139a-page 48 advanced information 1996 microchip technology inc. notes:
1996 microchip technology inc. advance information ds40139a-page 49 pic12c5xx 9.0 development support 9.1 de velopme nt t ools the pic16/17 microcontrollers are supported with a full range of hardware and software development tools: picmaster/picmaster ce real-time in-circuit emulator icepic low-cost pic16c5x and pic16cxx in-circuit emulator pro mate ? ii universal programmer picstart a plus entry-level prototype programmer picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board picdem-3 low-cost demonstration board mpasm assembler mplab-sim software simulator mplab-c (c compiler) fuzzy logic development system (fuzzytech a - mp) the pic12c508 and pic12c509 are supported by the systems shown in table 9-1. 9.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the pic12c5xx, pic16c5x, pic16cxx and pic17cxx families. picmaster is supplied with the mplab ? integrated development environment (ide), which allows editing, ?ake?and download, and source debugging from a single envi- ronment. interchangeable target probes allow the system to be easily recon?ured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new microchip micro- controllers. the picmaster emulator system has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x environment were chosen to best make these fea- tures available to you, the end user. a ce compliant version of picmaster is available for european union (eu) countries. 9.3 i cepic: lo w-cost pic16cxx in-cir cuit em ulator icepic is a low-cost in-circuit emulator solution for the microchip pic16c5x and pic16cxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 286-at a through pentium ? based machines under windows 3.x environment. icepic features real time, non-intrusive emulation. 9.4 pr o ma te ii: univer sal pr ogrammer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic16c5x, pic16cxx, pic17cxx and pic14000 devices. it can also set con?uration and code-protect bits in this mode. 9.5 p icst ar t plus entr y le vel de velopment system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and ef?ient. picstart plus is not recommended for production programming. picstart plus supports all pic16/17 devices with up to 40 pins. larger pin count devices such as the pic16c923 and pic16c924 may be supported with an adapter socket.
pic12c5xx ds40139a-page 50 advanced information 1996 microchip technology inc. 9.6 picdem-1 lo w-cost pic16/17 demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate ii or picstart-16b programmer, and easily test ?m- ware. the user can also connect the picdem-1 board to the picmaster emulator and down load the ?mware to the emulator for testing. additional pro- totype area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 9.7 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-16c, and easily test ?mware. the picmaster emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 9.8 picdem-3 lo w-cost pic16cxx demonstration boar d the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test ?mware. the picmaster emulator may also be used with the picdem-3 board to test ?m- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the pic- dem-3 board is an lcd panel, with 4 commons and 12 segments, that is capable of displaying time, tempera- ture and day of the week. the picdem-3 provides an additional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. picdem- 3 will be available in the 3rd quarter of 1996. 9.9 mplab integrated de velopment en vir onment software the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: a full featured editor three operating modes - editor - emulator - simulator a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es (either assembly or ?? one touch assemble (or compile) and download to pic16/17 tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e transfer data dynamically via dde (soon to be replaced by ole) run up to four emulators on the same pc the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 9.10 assemb ler (mp asm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic16c5x, pic16cxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers.
1996 microchip technology inc. advance information ds40139a-page 51 pic12c5xx mpasm allows full symbolic debugging from the micro chip universal emulator system (picmaster). mpasm has the following features to assist in develop- ing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the pic16/17. directives are helpful in making the development of your assemble source code shorter and more maintainable. 9.11 s oftware sim ulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the pic16/17 series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c and mpasm. the software simulator offers the low cost ?xibility to develop and debug code out- side of the laboratory environment making it an excel- lent multi-project software development tool. 9.12 c compiler ( mplab-c) the mplab-c code development system is a com- plete ? compiler and integrated development environ- ment for microchips pic16/17 family of microcontrollers. the compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display (picmaster emulator software versions 1.13 and later). 9.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 9.14 mp-drivew a y ? ?application code generator mp-driveway is an easy-to-use windows-based appli- cation code generator. with mp-driveway you can visually con?ure all the peripherals in a pic16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in c language. the output is fully compatible with micro- chips mplab-c c compiler. the code produced is highly modular and allows easy integration of your own code. mp-driveway is intelligent enough to maintain your code through subsequent code generation. 9.15 seev al a ev aluat i on and pr ogramming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can signi?antly reduce time-to-market and result in an optimized system. 9.16 t ruegaug e a intellig ent batter y mana g ement the truegauge development tool supports system development with the mta11200b truegauge intelli- gent battery management ic. system design veri?a- tion can be accomplished before hardware prototypes are built. user interface is graphically-oriented and measured data can be saved in a ?e for exporting to microsoft excel.
1996 microchip technology inc. advance information ds40139a-page 52 pic12c5xx table 9-1: development tools from microchip product ** mplab ? integrated development environment mplab ? c compiler mp-driveway applications code generator fuzzytech a -mp explorer/edition fuzzy logic dev. tool *** picmaster a / picmaster-ce in-circuit emulator icepic low-cost in-circuit emulator ****pro mate ? ii universal microchip programmer picstart a lite ultra low-cost dev. kit picstart a plus low-cost universal dev. kit pic12c508, 509 sw007002 sw006005 em167015/ em167101 dv007003 dv003001 pic14000 sw007002 sw006005 em147001/ em147101 dv007003 dv003001 pic16c52, 54, 54a, 55, 56, 57, 58a sw007002 sw006005 sw006006 dv005001/ dv005002 em167015/ em167101 em167201 dv007003 dv162003 dv003001 pic16c554, 556, 558 sw007002 sw006005 dv005001/ dv005002 em167033/ em167113 ? dv007003 dv003001 pic16c61 sw007002 sw006005 sw006006 dv005001/ dv005002 em167021/ n/a em167205 dv007003 dv162003 dv003001 pic16c62, 62a, 64, 64a sw007002 sw006005 sw006006 dv005001/ dv005002 em167025/ em167103 em167203 dv007003 dv162002 dv003001 pic16c620, 621, 622 sw007002 sw006005 sw006006 dv005001/ dv005002 em167023/ em167109 em167202 dv007003 dv162003 dv003001 pic16c63, 65, 65a, 73, 73a, 74, 74a sw007002 sw006005 sw006006 dv005001/ dv005002 em167025/ em167103 em167204 dv007003 dv162002 dv003001 pic16c642, 662* sw007002 sw006005 em167035/ em167105 ? dv007003 dv162002 dv003001 pic16c71 sw007002 sw006005 sw006006 dv005001/ dv005002 em167027/ em167105 em167205 dv007003 dv162003 dv003001 pic16c710, 711 sw007002 sw006005 sw006006 dv005001/ dv005002 em167027/ em167105 dv007003 dv162003 dv003001 pic16c72 sw007002 sw006005 sw006006 em167025/ em167103 dv007003 dv162002 dv003001 pic16f83 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 dv007003 dv162003 dv003001 pic16c84 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 em167206 dv007003 dv162003 dv003001 pic16f84 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 dv007003 dv162003 dv003001 pic16c923, 924* sw007002 sw006005 sw006006 dv005001/ dv005002 em167031/ em167111 dv007003 dv003001 pic17c42, 42a, 43, 44 sw007002 sw006005 sw006006 dv005001/ dv005002 em177007/ em177107 dv007003 dv003001 *contact microchip technology for availability date **mplab integrated development environment includes mplab-sim simulator and mpasm assembler ***all picmaster and picmaster-ce ordering part numbers above include pro mate ii programmer ****pro mate socket modules are ordered separately. see development systems ordering guide for specic ordering part numbers product truegauge a development kit seeval a designers kit hopping code security programmer kit hopping code security eval/demo kit all 2 wire and 3 wire serial eeprom's n/a dv243001 n/a n/a mta11200b dv114001 n/a n/a n/a hcs200, 300, 301 * n/a n/a pg306001 dm303001
pic12c5xx ds40139a-page 53 advance information 1996 microchip technology inc. 10.0 electrical characteristics - pic12c5xx absolute maximum ratings? ambient temperature under bias ............................................................................................................. ?0?c to +85?c storage temperature.............................................................................................................................. ?5?c to +150?c voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5 v voltage on mclr with respect to v ss (2) .......................................................................................................... 0 to +14 v voltage on all other pins with respect to v ss ............................................................................... ?.6 v to (v dd + 0.6 v) total power dissipation (1) ................................................................................................................................... 700 mw max. current out of v ss pin.................................................................................................................................. 200 ma max. current into v dd pin .................................................................................................................................... 150 ma max. current into v dd pin (vclamp active)........................................................................................................... 100 ma input clamp current, i ik (v i < 0 or v i > v dd ) ..................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................. 20 ma max. output current sunk by any i/o pin ............................................................................................................... 25 ma max. output current sourced by any i/o pin.......................................................................................................... 25 ma max. output current sourced by i/o port (porta).............................................................................................. 100 ma max. output current sourced by i/o port with v dd clamp active(porta)............................................................. 50 ma max. output current sunk by i/o port (porta ) .................................................................................................. 100 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v ol x i ol ) note 2: voltage spikes below vss at the mclr pin, inducing currents greater than 80 ma may cause latch-up. thus, a series resistor of 50 to 100w should be used when applying a low level to the mclr pin rather than pulling this pin directly to vss. ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic12c5xx ds40139a-page 54 advance information 1996 microchip technology inc. 10.1 dc characteristics: pic12508/509 (commercial) pic12508/509 (industrial) dc characteristics power supply pins standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial) ?0 c t a +85 c (industrial) characteristic sym min typ (1) max units conditions supply voltage v dd 2.5 5.5 v f osc = dc to 4 mhz ram data retention voltage (2) v dr 1.5* v device in sleep mode v dd start voltage to ensure power-on reset v por v ss v see section on power-on reset for details v dd rise rate to ensure power-on reset s vdd 0.05* v/ms see section on power-on reset for details supply current (3) i dd 1.8 1.8 15 19 2.4 2.4 27 35 ma ma m a m a xt and extrc options (note 4) f osc = 4 mhz, v dd = 5.5 v intrc option f osc = 4 mhz, v dd = 5.5 v lp o ption , commercial temperature f osc = 32 khz, v dd = 3.0 v, wdt disabled lp o ption , industrial temperature f osc = 32 khz, v dd = 3.0 v, wdt disabled power-down current (5) wdt enabled wdt disabled i pd 4 5 0.25 0.3 12 14 4 5 m a m a m a m a v dd = 3.0 v, commercial v dd = 3.0 v, industrial v dd = 3.0 v, commercial v dd = 3.0 v, industrial * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guid- ance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in kohm. 5: the power down current in sleep mode does not depend on the oscillator type. power down current is mea- sured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss .
1996 microchip technology inc. advance information ds40139a-page 55 pic12c5xx 10.2 dc characteristics: pic12508/509 (commercial) pic12508/509 (industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial) ?0 c t a +85 c (industrial) operating voltage v dd range is described in section 10.1. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr osc1 osc1 v il v ss v ss v ss v ss 0.2 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v pin at hi-impedance extrc option only (4) xt and lp options input high voltage i/o ports mclr (schmitt trigger) osc1 (schmitt trigger) v ih 2.0 0.2v dd +1v 0.85 v dd 0.85 v dd 0.7 v dd v dd v dd v dd v dd v dd v v v v v 4.0 v< v dd 5.5 v (5) full v dd range (5) extrc option only (4) xt and lp options input leakage current (2,3) i/o ports mclr osc1 i il ? 20 ? 0.5 130 0.5 0.5 +1 250 +5 +3 m a m a m a m a for v dd 5.5 v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25 v (2) v pin = v dd v ss v pin v dd , xt and lp options output low voltage i/o ports vol 0.6 v i ol = 8.7 ma, v dd = 4.5 v output high voltage (3,4) i/o ports v oh v dd ?.7 v i oh = ?.4 ma, v dd = 4.5 v * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guid- ance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 3: negative current is de?ed as coming out of the pin. 4: for pic12c5xx devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic12c5xx be driven with external clock in rc mode. 5: the user may use the better of the two speci?ations.
pic12c5xx ds40139a-page 56 advance information 1996 microchip technology inc. 10.3 timing p arameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2 to mc mclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance figure 10-1: load conditions - pic12c5xx c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1
1996 microchip technology inc. advance information ds40139a-page 57 pic12c5xx 10.4 timing dia grams and speci cations figure 10-2: external clock timing - pic12c5xx table 10-1: external clock timing requirements - pic12c5xx ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc 4 mhz extrc osc mode dc 4 mhz xt osc mode dc 200 khz lp osc mode oscillator frequency (2) dc 4 mhz extrc osc mode 0.1 4 mhz xt osc mode dc 200 khz lp osc mode 1t osc external clkin period (2) 250 ns extrc osc mode 250 ns xt osc mode 5 ms lp osc mode oscillator period (2) 250 ns extrc osc mode 250 10,000 ns xt osc mode 5 ms lp osc mode 2tcy instruction cycle time (3) 4/f osc 3 tosl, tosh clock in (osc1) low or high time 50* ns xt oscillator 2* ms lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time 25* ns xt oscillator 50* ns lp oscillator * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all speci?d values are based on characterization data for that particular oscillator type under standard oper- ating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?ax?cycle time limit is ?c?(no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 q4 q1 q2 q3 q4 q1 133 44 2
pic12c5xx ds40139a-page 58 advance information 1996 microchip technology inc. figure 10-3: i/o timing - pic12c5xx table 10-2: timing requirements - pic12c5xx ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial) ?0 c t a +85 c (industrial) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min typ (1) max units 17 tosh2iov osc1 - (q1 cycle) to port out valid (3) 100* ns 18 tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19 tiov2osh port input valid to osc1 - (i/o in setup time) tbd ns 20 tior port output rise time (3) 10 25** ns 21 tiof port output fall time (3) 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical (?yp? column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in extrc mode. 3: see figure 10-1 for loading conditions. osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old value new value note: all tests must be done with speci?d capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19
1996 microchip technology inc. advance information ds40139a-page 59 pic12c5xx figure 10-4: reset, watchdog timer, and device reset timer timing - pic12c5xx table 10-3: reset, watchdog timer, and device reset timer - pic12c5xx ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial) ?0 c t a +85 c (industrial) operating voltage v dd range is described in section 10.1 parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 2000* ns v dd = 5 v 31 twdt watchdog timer time-out period (no prescaler) 9* 18* 30* ms v dd = 5 v (commercial) 32 t drt device reset timer period (2) 9* 18* 30* ms v dd = 5 v (commercial) 34 tio z i/o hi-impedance from mclr low 100* ns * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested 2: drt runs only on power-up and in normal execution in extrc and intrc modes, and never runs in test modes. (i.e. does not run on wake-up from sleep) v dd mclr internal por drt timeout internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30 (note 2) 2: runs in mclr or wdt reset only in xt and lp modes.
pic12c5xx ds40139a-page 60 advance information 1996 microchip technology inc. figure 10-5: timer0 clock timings - pic12c5xx table 10-4: timer0 clock requirements - pic12c5xx table 10-5: mclr pull-up resistor ranges ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial) ?0 c t a +85 c (industrial) operating voltage v dd range is described in section 10.1. parameter no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 42 tt0p t0cki period 20 or t cy + 40 * n ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd (volts) temperature ( c) min typ max units 2.5 -40 43* 66 100* k w 2.5 25 47* 74 111* k w 2.5 85 50* 79 119* k w 5.5 -40 25 36 48 k w 5.5 25 30* 42 56* k w 5.5 85 32 46 63 k w * these parameters are characterized but not tested. t0cki 40 41 42
1996 microchip technology inc. advance information ds40139a-page 61 pic12c5xx figure 10-6: calibrated internal rc frequency range vs. temperature (v dd = 5.5v) figure 10-7: calibrated internal rc frequency range vs. temperature (v dd = 2.5v) temperature ( c) frequency (mhz) -40 25 85 3.5 4.0 4.5 note: altering calibration value by 1 is approximately a 4ns change. temperature ( c) frequency (mhz) -40 25 85 3.5 4.0 4.5 note: altering calibration value by 1 is approximately a 4ns change. typical
pic12c5xx ds40139a-page 62 advance information 1996 microchip technology inc. figure 10-8: calibrated internal rc frequency range vs. v dd at temperature = -40 c figure 10-9: calibrated internal rc frequency range vs. v dd at temperature = 25 c v dd frequency (mhz) 2.5 3.5 5.5 3.5 4.0 4.5 note: altering calibration value by 1 is approximately a 4ns change. 4.5 v dd frequency (mhz) 2.5 3.5 5.5 3.5 4.0 4.5 note: altering calibration value by 1 is approximately a 4ns change. 4.5
1996 microchip technology inc. advance information ds40139a-page 63 pic12c5xx figure 10-10: calibrated internal rc frequency range vs. v dd at temperature = 85 c v dd frequency (mhz) 2.5 3.5 5.5 3.5 4.0 4.5 note: altering calibration value by 1 is approximately a 4ns change. 4.5
pic12c5xx ds40139a-page 64 advance information 1996 microchip technology inc. notes:
1996 microchip technology inc. advance information ds40139a-page 65 pic12c5xx 11.0 packaging information 11.1 p ac ka g e marking inf ormation 8-lead pdip (300 mil) example legend: mm...m microchip part number information xx...x customer speci? information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a., s = tempe, arizona, u.s.a. d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. 8-lead soic (200 mil) example to be determined to be determined
pic12c5xx ds40139a-page 66 advance information 1996 microchip technology inc. 11.2 8-lead plastic dual in-line (300 mil) package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 4.064 0.160 a1 0.381 0.015 a2 3.048 3.810 0.120 0.150 b 0.355 0.559 0.014 0.022 b1 1.397 1.651 0.055 0.065 c 0.203 0.381 typical 0.008 0.015 typical d 9.017 10.922 0.355 0.430 d1 7.620 7.620 reference 0.300 0.300 reference e 7.620 8.255 0.300 0.325 e1 6.096 7.112 0.240 0.280 e1 2.489 2.591 typical 0.098 0.102 typical ea 7.620 7.620 reference 0.300 0.300 reference eb 7.874 9.906 0.310 0.390 l 3.048 3.556 0.120 0.140 n88 88 s 0.889 0.035 s1 0.254 0.010 a c e a e b n pin no. 1 indicator area e1 e s s1 d b1 b e1 d1 a1 a2 a l base plane seating plane
1996 microchip technology inc. advance information ds40139a-page 67 pic12c5xx 11.3 8-lead plastic surface mount (soic - medium, 200 mil bod y) package group: plastic soic (sm) symbol millimeters inches min max notes min max notes a 0 8 0 8 a 1.778 2.00 0.070 0.079 a1 0.101 0.249 0.004 0.010 b 0.355 0.483 0.014 0.019 c 0.190 0.249 0.007 0.010 d 5.080 5.334 0.200 0.210 e 5.156 5.411 0.203 0.213 e 1.270 1.270 reference 0.050 0.050 reference h* 7.670 8.103 0.302 0.319 h 0.381 0.762 0.015 0.030 l 0.508 1.016 0.020 0.040 n 1414 1414 cp 0.102 0.004 b e n index area chamfer h x 45 a e h 1 2 3 cp h x 45 c l seating plane base plane d a1 a
pic12c5xx ds40139a-page 68 advance information 1996 microchip technology inc. notes:
1996 microchip technology inc. advance information ds40139a-page 69 pic12c5xx appendix a:pic16/17 microcontrollers table a-1: pic14xxx devices pic14000 20 4k 192 tmr0 adtmr i 2 c/ smd 14 11 22 2.7-6.0 yes internal oscillator, bandgap reference, temperature sensor, calibration factors, low voltage detector, sleep, hibernate, comparators with programmable references (2) 28-pin dip, soic, ssop (.300 mil) maximum frequency of operation (mhz) data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port slope a/d converter interrupt sources i/o pins voltage range (volts) brown-out reset eprom program memory (x14 words) clock memory peripherals features in-circuit serial programming additional on-chip features packages (high-res) channels
pic12c5xx ds40139a-page 70 advance information 1996 microchip technology inc. table a-2: pic16c5x family of devices pic16c52 4 384 25 tmr0 12 2.5-6.25 33 18-pin dip, soic pic16c54 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16c55 20 512 24 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c56 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c57 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57b 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c58a 20 2k 73 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. packages number of instructions voltage range (volts) i/o pins timer module(s) ram data memory (bytes) (x12 words) program memory rom eprom maximum frequency of operation (mhz) features peripherals memory clock
1996 microchip technology inc. advance information ds40139a-page 71 pic12c5xx table a-3: pic16cxxx family of devices pic16c554 20 512 80 tmr0 ? 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c556 20 1k 80 tmr0 3 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c558 20 2k 128 tmr0 3 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c620 20 512 80 tmr0 2 yes 4 13 2.5-6.0 yes 18-pin dip, soic; 20-pin ssop pic16c621 20 1k 80 tmr0 2 yes 4 13 2.5-6.0 yes 18-pin dip, soic; 20-pin ssop pic16c622 20 2k 128 tmr0 2 yes 4 13 2.5-6.0 yes 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c6xxx family devices use serial programming with clock pin rb6 and data pin rb7. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) comparator(s) internal reference voltage interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features (x14 words)
pic12c5xx ds40139a-page 72 advance information 1996 microchip technology inc. table a-4: pic16c6x family of devices pic16c62 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 2.5-6.0 yes 28-pin sdip, soic, ssop pic16c62a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16cr62 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16c63 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 10 22 2.5-6.0 yes yes 28-pin sdip, soic pic16cr63 (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 10 22 2.5-6.0 yes yes 28-pin sdip, soic pic16c64 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 2.5-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c64a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16cr64 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16c65 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 2.5-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c65a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16cr65 (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16c6x family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features rom in-circuit serial programming (x14 words)
1996 microchip technology inc. advance information ds40139a-page 73 pic12c5xx table a-5: pic16c7x family of devices pic16c710 20 512 36 tmr0 4 4 13 2.5-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c71 20 1k 36 tmr0 4 4 13 2.5-6.0 yes 18-pin dip, soic pic16c711 20 1k 68 tmr0 4 4 13 2.5-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c72 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 5 8 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16c73 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 2.5-6.0 yes 28-pin sdip, soic pic16c73a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 2.5-6.0 yes yes 28-pin sdip, soic pic16c74 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 2.5-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c74a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c7x family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom program memory (x14 words) data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages clock memory peripherals features in-circuit serial programming
pic12c5xx ds40139a-page 74 advance information 1996 microchip technology inc. table a-6: pic16c8x family of devices pic16c84 10 1k 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16f84 (1) 10 1k 68 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16cr84 (1) 10 1k 68 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16f83 (1) 10 512 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16cr83 (1) 10 512 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16c8x family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eeprom data eeprom (bytes) data memory (bytes) timer module(s) interrupt sources i/o pins voltage range (volts) packages program memory clock memory peripherals features rom flash
1996 microchip technology inc. advance information ds40139a-page 75 pic12c5xx table a-7: pic16c9xx family of devices pic16c923 8 4k 176 tmr0, tmr1, tmr2 1 spi/i 2 c 4 com 32 seg 8 25 27 3.0-6.0 yes 64-pin sdip (1) , tqfp, 68-pin plcc, die pic16c924 8 4k 176 tmr0, tmr1, tmr2 1 spi/i 2 c 5 4 com 32 seg 9 25 27 3.0-6.0 yes 64-pin sdip (1) , tqfp, 68-pin plcc, die all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local microchip representative for availability of this package. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features in-circuit serial programming input pins lcd module
pic12c5xx ds40139a-page 76 advance information 1996 microchip technology inc. table a-8: pic17cxx family of devices pic17c42 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 4.5-5.5 55 40-pin dip; 44-pin plcc, mqfp pic17c42a 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-5.5 58 40-pin dip; 44-pin plcc, mqfp pic17cr42 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-5.5 58 40-pin dip; 44-pin plcc, mqfp pic17c43 25 4k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17cr43 25 4k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17c44 25 8k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. maximum frequency of operation (mhz) eprom ram data memory (bytes) timer module(s) captures serial port(s) (usart) external interrupts interrupt sources i/o pins voltage range (volts) number of instructions packages clock memory peripherals features pwms hardware multiply program memory (w ords) rom
1996 microchip technology inc. advance information ds40139a-page 77 pic12c5xx pin compatibility devices that have the same package type and v dd , v ss and mclr pin locations are said to be pin compatible. this allows these different devices to operate in the same socket. compatible devices may only requires minor software modi?ation to allow proper operation in the application socket (ex., pic16c56 and pic16c61 devices). not all devices in the same package size are pin compatible; for example, the pic16c62 is compatible with the pic16c63, but not the pic16c55. pin compatibility does not mean that the devices offer the same features. as an example, the pic16c54 is pin compatible with the pic16c71, but does not have an a/d converter, weak pull-ups on portb, or interrupts. table a-9: pin compatible devices pin compatible devices package pic12c508, pic12c509 8-pin pic16c54, pic16c54a, pic16cr54a, pic16c56, pic16c58a, pic16cr58a, pic16c61, pic16c554, pic16c556, pic16c558 pic16c620, pic16c621, pic16c622, pic16c710, pic16c71, pic16c711, pic16c83, pic16cr83, pic16c84, pic16c84a, pic16cr84 18-pin (20-pin) pic16c55, pic16c57, pic16cr57b 28-pin pic16c62, pic16cr62, pic16c62a, pic16c63, pic16c72, pic16c73, pic16c73a 28-pin pic16c64, pic16cr64, pic16c64a, pic16c65, pic16c65a, pic16c74, pic16c74a 40-pin pic17c42, pic17c43, pic17c44 40-pin
pic12c5xx ds40139a-page 78 advance information 1996 microchip technology inc. notes:
1996 microchip technology inc. advance information ds40139a-page 79 pic12c5xx index a alu ...................................................................................... 7 applications.......................................................................... 3 architectural overview ......................................................... 7 assembler .......................................................................... 50 b block diagram on-chip reset circuit ................................................ 30 timer0........................................................................ 21 tmr0/wdt prescaler................................................ 24 watchdog timer......................................................... 33 brown-out protection circuit ............................................. 34 c c compiler (mp-c) ............................................................ 51 carry .................................................................................... 7 clocking scheme ............................................................... 10 code protection ........................................................... 25, 35 configuration bits............................................................... 25 configuration word pic16c54a/cr57a/c58a ......................................... 25 d development support ........................................................ 49 development tools ............................................................ 49 device varieties ................................................................... 5 digit carry ............................................................................ 7 f family of devices pic14xxx.................................................................. 69 pic16c5x .................................................................. 70 pic16c62x ................................................................ 71 pic16c7x .................................................................. 73 pic16c8x .................................................................. 74 features............................................................................... 1 fsr.................................................................................... 17 fuzzy logic dev. system ( fuzzy tech a -mp) .............. 49, 51 i i/o interfacing .................................................................... 19 i/o ports............................................................................. 19 i/o programming considerations....................................... 20 id locations ................................................................. 25, 35 indf................................................................................... 17 indirect data addressing.................................................... 17 instruction cycle ................................................................ 10 instruction flow/pipelining ................................................. 10 instruction set summary.................................................... 38 l loading of pc .................................................................... 16 m memory organization......................................................... 11 data memory ............................................................. 12 program memory ....................................................... 11 mpasm assembler...................................................... 49, 50 mp-c c compiler ............................................................... 51 mpsim software simulator.......................................... 49, 51 o one-time-programmable (otp) devices............................ 5 option register............................................................... 15 osc selection ................................................................... 25 oscillator configurations.................................................... 26 oscillator types hs .............................................................................. 26 lp............................................................................... 26 rc .............................................................................. 26 xt ............................................................................... 26 p package marking information............................................. 65 packaging information........................................................ 65 pc....................................................................................... 16 picdem-1 low-cost pic16/17 demo board ............... 49, 50 picdem-2 low-cost pic16cxx demo board............. 49, 50 picdem-3 low-cost pic16c9xxx demo board .............. 50 picmaster ? rt in-circuit emulator ............................... 49 picstart ? low-cost development system.................... 49 pin compatible devices ..................................................... 77 por device reset timer (drt) ................................... 25, 32 pd ............................................................................... 34 power-on reset (por).............................................. 25 to ............................................................................... 34 porta ............................................................................... 19 power-down mode ............................................................. 35 prescaler ............................................................................ 24 pro mate ? universal programmer ................................. 49 program counter ................................................................ 16 q q cycles.............................................................................. 10 r rc oscillator ...................................................................... 27 read modify write .............................................................. 20 register file map pic16c54a/cr54a/cr54b/cr56 ............................. 12 pic16c58a/cr58a/cr58b ....................................... 12 registers special function ......................................................... 13 reset .................................................................................. 25 reset on brown-out ........................................................... 34 s sleep .......................................................................... 25, 35 software simulator (mpsim) .............................................. 51 special features of the cpu .............................................. 25 special function registers................................................. 13 stack................................................................................... 16 status ............................................................................... 7 status register ............................................................... 14 t timer0 switching prescaler assignment ................................ 24 timer0 ........................................................................ 21 timer0 (tmr0) module .............................................. 21 tmr0 with external clock .......................................... 23 timing diagrams and specifications .................................. 57 timing parameter symbology and load conditions .......... 56 tris registers ................................................................... 19 w wake-up from sleep ........................................................ 35 watchdog timer (wdt)................................................ 25, 32 period ......................................................................... 33 programming considerations ..................................... 33 z zero bit ................................................................................. 7 this document was created with framemake r404
pic12c5xx ds40139a-page 80 advanced information 1996 microchip technology inc. list of examples example 3-1: instruction pipeline flow ............................ 10 example 4-1: indirect addressing .................................... 17 example 4-2: how to clear ram using indirect addressing................................................. 17 example 5-1: read-modify-write instructions on an i/o port ...................................................... 20 example 6-1: changing prescaler (timer0 ? wdt .........) 24 example 6-2: changing prescaler (wdt ? timer0 .........) 24 list of figures figure 3-1: pic12c5xx block diagram ......................... 8 figure 3-2: clock/instruction cycle .............................. 10 figure 4-1: program memory map and stack for the pic12c5xx ............................................... 11 figure 4-2: pic12c508 register file map ................... 12 figure 4-3: pic12c509 register file map ................... 12 figure 4-4: status register (address:03h)............... 14 figure 4-5: option register....................................... 15 figure 4-6: loading of pc branch instructions - pic12c508/c509....................................... 16 figure 4-7: direct/indirect addressing.......................... 17 figure 5-1: equivalent circuit for a single i/o pin........ 19 figure 5-2: successive i/o operation .......................... 20 figure 6-1: timer0 block diagram ............................... 21 figure 6-2: timer0 timing: internal clock/ no prescale ............................................... 22 figure 6-3: timer0 timing: internal clock/ prescale 1:2............................................... 22 figure 6-4: timer0 timing with external clock ........... 23 figure 6-5: block diagram of the timer0/ wdt prescaler .......................................... 24 figure 7-1: configuration word for pic12c508 or pic12c509 ................................................ 25 figure 7-2: crystal operation (or ceramic resonator) (xt or lp osc configuration) ................... 26 figure 7-3: external clock input operation (xt or lp osc configuration) ................... 26 figure 7-4: external parallel resonant crystal oscillator circuit......................................... 27 figure 7-5: external series resonant crystal oscillator circuit ......................................... 27 figure 7-6: rc oscillator mode.................................... 28 figure 7-7: mclr select.............................................. 29 figure 7-8: simplified block diagram of on-chip reset circuit................................ 30 figure 7-9: time-out sequence on power-up (mclr pulled low).................................... 31 figure 7-10: time-out sequence on power-up (mclr tied to vdd): fast vdd rise time . 31 figure 7-11: time-out sequence on power-up (mclr tied to v dd ): slow vdd rise time 31 figure 7-12: watchdog timer block diagram ................ 33 figure 7-13: brown-out protection circuit 1 .................. 34 figure 7-14: brown-out protection circuit 2 .................. 34 figure 7-15: typical in-circuit serial programming connection................................................. 36 figure 8-1: general format for instructions ................. 37 figure 10-1: load conditions - pic12c5xx .................. 56 figure 10-2: external clock timing - pic12c5xx ......... 57 figure 10-3: i/o timing - pic12c5xx........................... 58 figure 10-4: reset, watchdog timer, and device reset timer timing - pic12c5xx ............. 59 figure 10-5: timer0 clock timings - pic12c5xx ......... 60 figure 10-6: calibrated internal rc frequency range vs. temperature (v dd = 5.5v)........ 61 figure 10-7: calibrated internal rc frequency range vs. temperature (v dd = 2.5v)................... 61 figure 10-8: calibrated internal rc frequency range vs. v dd at temperature = -40 c ............... 62 figure 10-9: calibrated internal rc frequency range vs. v dd at temperature = 25 c................. 62 figure 10-10: calibrated internal rc frequency range vs. v dd at temperature = 85 c................ 63 list of tables table 1-1: pic12c5xx family of devices.................... 4 table 3-1: pic12c5xx pinout description................... 9 table 4-1: special function register summary ......... 13 table 5-1: summary of port registers ....................... 19 table 6-1: registers associated with timer0 ............ 22 table 7-1: capacitor selection for ceramic resonators - pic12c5xx ......................... 26 table 7-2: capacitor selection for crystal oscillator - pic12c5xx............................. 26 table 7-3: reset conditions for registers ................ 28 table 7-4: reset condition for special registers ..... 29 table 7-5: summary of registers associated with the watchdog timer .................................. 33 table 7-6: to /pd/gpwuf status after reset........... 34 table 7-7: events affecting to /pd status bits .......... 34 table 8-1: opcode field descriptions ..................... 37 table 8-2: instruction set summary ........................... 38 table 9-1: development tools from microchip.......... 52 table 10-1: external clock timing requirements - pic12c5xx ............................................... 57 table 10-2: timing requirements - pic12c5xx.......... 58 table 10-3: reset, watchdog timer, and device reset timer - pic12c5xx ........................ 59 table 10-4: timer0 clock requirements - pic12c5xx ............................................... 60 table 10-5: mclr pull-up resistor ranges ................ 60
1996 microchip technology inc. advance information ds40139a-page 81 pic12c5xx on-line support microchip provides two methods of on-line support. these are the microchip bbs and the microchip world wide web (www) site. use microchip's bulletin board service (bbs) to get current information and help about microchip products. microchip provides the bbs communication channel for you to use in extending your technical staff with microcontroller and memory experts. to provide you with the most responsive service possi- ble, the microchip systems team monitors the bbs, posts the latest component data and software tool updates, provides technical help and embedded sys- tems insights, and discusses how microchip products provide project solutions. the web site, like the bbs, is used by microchip as a means to make ?es and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favor ite internet browser to attach to: www.microchip.com the ?e transfer site is available by using an ftp ser- vice to connect to: ftp.mchip.com/biz/mchip the web site and ?e transfer site provide a variety of services. users may download ?es for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip speci? business information is also available, including listings of microchip sales of?es, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products connecting to the microchip bbs connect worldwide to the microchip bbs using either the internet or the compuserve communications net- work. internet: you can telnet or ftp to the microchip bbs at the address: mchipbbs.microchip.com compuser ve comm unications netw ork: when using the bbs via the compuserve network, in most cases, a local call is your only expense. the microchip bbs connection does not use compuserve membership services, therefore you do not need compuserve membership to join microchip's bbs. there is no charge for connecting to the microchip bbs. the procedure to connect will vary slightly from country to country. please check with your local compuserve agent for details if you have a problem. compuserve service allow multiple users various baud rates depending on the local point of access. the following connect procedure applies in most loca- tions. 1. set your modem to 8-bit, no parity, and one stop (8n1). this is not the normal compuserve setting which is 7e1. 2. dial your local compuserve access number. 3. depress the key and a garbage string will appear because compuserve is expecting a 7e1 setting. 4. type +, depress the key and ?ost name: will appear. 5. type mchipbbs, depress the key and you will be connected to the microchip bbs. in the united states, to ?d the compuserve phone number closest to you, set your modem to 7e1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. after the system responds with ?ost name:? type network, depress the key and follow compuserve's directions. for voice information (or calling from overseas), you may call (614) 723-1550 for your local compuserve number. microchip regularly uses the microchip bbs to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for microchip systems software products. for each sig, a moderator monitors, scans, and approves or disap- proves ?es submitted to the sig. no executable ?es are accepted from the user community in general to limit the spread of computer viruses. systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picstart, picmaster, and are registered trademarks of microchip technology incorporated in the u.s.a. and other coun- tries. flex rom, mplab, pro mate, and fuzzy lab, are trademarks and sqtp is a service mark of microchip in the u.s.a. fuzzy tech is a registered trademark of inform software corporation. ibm, ibm pc-at are registered trademarks of international business machines corp. pentium is a trademark of intel corporation. windows is a trademark and ms-dos, microsoft windows are registered trade- marks of microsoft corporation. compuserve is a regis- tered trademark of compuserve incorporated. all other trademarks mentioned herein are the property of their respective companies. this document was created with framemake r404
pic12c5xx ds40139a-page 82 advance information 1996 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you ?d the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds40139a pic12c5xx
1996 microchip technology inc. advance information ds40139a-page 83 pic12c5xx pic12c5xx product identification system please contact your local sales of?e for exact ordering procedures. pattern: special requirements package: sm = 200 mil soic p = 300 mil pdip temperature range: -=0 c to +70 c i = -40 c to +85 c frequency range: 04 = 4 mhz device pic12c508 pic12c509 pic12c508t (tape & reel for soic only) pic12c509t (tape & reel for soic only) part no. -xx x /xx xxx examples a) pic12c508-04/p commercial temp., pdip package, 4 mhz, normal v dd limits b) pic12c508-04i/sm industrial temp., soic package, 4 mhz, normal v dd limits c) pic12c509-04i/p industrial temp., pdip package, 4 mhz, normal v dd limits sales and suppor t products supported by a preliminary data sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: your local microchip sales of?e (see below) the microchip corporate literature center u.s. fax: (602) 786-7277 the microchips bulletin board, via your local compuserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using. for latest version information and upgrade kits for microchip development tools, please call 1-800-755-2345 or 1-602-786-7302. 1. 2. 3.
ds40139a - page 84 1996 microchip technology inc. w orldwide s ales & s ervice all rights reserved. 1996, microchip technology incorporated, usa. americas (continued) new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905 405-6279 fax: 905 405-6253 asia/pacific hong kong microchip technology rm 3801b, tower two metroplaza, 223 hing fong road, kwai fong, n.t., hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 1 628 850303 fax: 44 1 628 850178 france arizona microchip technology sarl zone industrielle de la bonde 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041, agrate brianza, milan italy tel: 39 39 689 9939 fax: 39 39 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 5/10/96 americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.microchip.com/ atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology inc. suite 150 two prestige place miamisburg, oh 45342 tel: 513 291-1654 fax: 513 291-9175 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies.

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